Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit--a simple, state-preserving, low-leakage circuit that relies on voltage scaling for leakage reduction-can be used to reduce the total energy consumption of data caches by more than 50%. In this paper, we extend the architectural control mechanism of the drowsy cache to reduce leakage power consumption of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. To enable drowsy instruction caches, we propose a technique called cache subbank prediction which is used to selectively wake up only the necessary parts of the i...

• Type: Journal
• Year: 2002
• Where: MICRO
• Authors: Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
• Keywords: Drowsy, Hardware, Instruction Cache, MICRO 2002, Power Consumption