Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory

This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major challenge in the packet memory controller design is to make the design scalable. As the input and output bandwidth requirement and the number of output queues for routers increase, the memory system becomes a bottleneck that limits the performance and scalability. Existing schemes require an input and output buffer that store packet data temporarily before they are written into or read from the memory. With the buffer size proportional to the number of output queues, the buffer becomes a limiting factor for scalability. Our scheme consists of a hashing logic and a reorder buffer whose size is not proportional to the number of output queues and is scalable with the increasing number of output queues. Another major challenge in the packet memory controller design is supporting QoS. As an increasing number of intern...

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Hyuk-Jun Lee, Eui-Young Chung
• Keywords: Memory Controller, Output Queues, Packet Memory, TVLSI 2008