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Sci2ools
ISCAS
2005
IEEE
2005
IEEE
A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch
Real-time Traffic| Added | 25 Jun 2010 |
| Updated | 25 Jun 2010 |
| Type | Conference |
| Year | 2005 |
| Where | ISCAS |
| Authors | Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun |
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