In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the'FFT processor can operateon a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementationsof ConvergentBlock FloatingPoint (CBFP), the memory requirementscan be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35pm standard CMOS technology. In netlist simulations, the FFT processor is capable of calculatinga 2048 complexpoint FFT or IFFT in 27ps with a maximum clock frequency of 76MHz.