Accurate rise time and overshoots estimation in RLC interconnects

A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the rise time decreases as the inductance effect increases. Also, a closed form expression for the maximum percentage overshoots is introduced that is within 5% error of dynamic circuit simulations. The expressions introduced here are analytical and differentiable over all damping conditions. Hence, these solutions are suitable for design and optimization tools.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Noha H. Mahmoud, Yehea I. Ismail
• Keywords: Closed Form Expression, Dynamic Circuit Simulations, ISCAS 2003, Rise Time