An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing

Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be eliminated. For this type of sharing, called migratory sharing, each processor typically causes a cache miss followed by an invalidation request which could be merged with the preceding cache-miss request. In this paper we propose an adaptive protocol that invokes this optimization dynamically for migratory blocks. For other blocks, the protocol works as an ordinary write-invalidate protocol. We show that the protocol is a simple extension to a write-invalidate protocol. Based on a program-driven simulation model of an architecture similar to the Stanford DASH, and a set of four benchmarks, we evaluate the potential performance improvements of the protocol. We find that it effectively eliminates most single invalidations which improves the performance by reducing the shared access penalty and the network traffic....

• Type: Conference
• Year: 1993
• Where: ISCA
• Authors: Per Stenström, Mats Brorsson, Lars Sandberg
• Keywords: Adaptive Protocol, Hardware, ISCA 1993, Ordinary Write-invalidate Protocol, Write-invalidate Protocol