Adaptive Spill-Receive for robust high-performance caching in CMPs

In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in response to the requirement of individual cores. Capacity sharing can be provided in private caches by spilling a line evicted from one cache to another cache. However, naively allowing all caches to spill evicted lines to other caches have limited performance benefit as such spilling does not take into account which cores benefit from extra capacity and which cores can provide extra capacity. This paper proposes Dynamic Spill-Receive (DSR) for efficient capacity sharing. In a DSR architecture, each cache uses Set Dueling to learn whether it should act as a "spiller cache" or "receiver cache" for best overall performance. We evaluate DSR for a Quad-core system with 1MB private caches using 495 multi-programmed workloads. DSR improves average throughput by 18% (weighted-speedup by 13% and ha...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Moinuddin K. Qureshi
• Keywords: Cache Capacity, Computer Architecture, HPCA 2009, Private Caches, Spiller Cache