Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions

While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the layout introducing systematic variations to the simulated and verified performance. As a result, actual on-silicon chip performance is quite different from sign-off expectations. This paper presents a new methodology to provide better estimates of on-silicon performance. The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and speed path characterization. This approach is applied to a state-of-theart microprocessor and contrasted with traditional design flow practices where ideal (i.e., drawn) Lgate values are employed, leading to a subsequent lack of predictive power. We present a platform for diagnosing and improving OPC quality on gates with specific functionality ...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
• Keywords: Accurate Timing Analysis, DAC 2005, Design Automation, Design Flow, Residual Opc Errors