Algorithm Transformation for FPGA Implementation

— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimised to run on a serial processor. To obtain an efficient hardware architecture, one that makes use of the available parallelism, the algorithms need to be transformed. Eleven such transformations are identified and explained. While some of these are straightforward, and have been implemented by some compilers, many cannot be automated because they require detailed knowledge of the algorithm. Keywords- FPGA, algorithm, architecture, automated design, compilation, hardware description languages

• Type: Conference
• Year: 2010
• Where: DELTA
• Authors: Donald G. Bailey, Christopher T. Johnston
• Keywords: DELTA 2010, FPGA Based Hardware, Hardware Description Languages, Level Hardware Description