Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces

Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software developers for program optimization, performance tuning, and debugging. Such traces are typically very large and need to be compressed to reduce the storage, processing, and communication bandwidth requirements. However, preexisting general-purpose and trace-specific compression algorithms are designed for software implementation and are not suitable for runtime compression. Compressing program execution traces at runtime in hardware can deliver insights into the behavior of the system under test without any negative interference with normal program execution. Traditional debugging tools, on the other hand, have to stop the program frequently to examine the state of the processor. Moreover, software developers often do not have access to the entire history of computation that led to an erroneous state. In addit...

• Type: Conference
• Year: 2007
• Where: DCC
• Authors: Milena Milenkovic, Aleksandar Milenkovic, Martin Burtscher
• Keywords: Compression Ratio, Computer Graphics, Data Address Traces, DCC 2007, On-chip Trace Compression