Analog property checkers: a DDR2 case study

Abstract Modeling and Simulation Aided Verification of Analog/MixedSignal Circuits S. Little and C. Myers (University of Utah, USA) Monday, July 14, 14:00-17:00 4 14:00-14:40 fSpice: A Boolean Satisfiability Based Approach to Formally Verifying Analog Circuits S.K. Tiwary, A. Gupta, J.R. Phillips, C. Pinello and R. Zlatanovici (Cadence Research Labs, USA) 5 14:40-15:20 Statistical Model Checking of Mixed-Analog Circuits E. Clarke, A. Donze and A. Legay (Carnegie Mellon University, USA) Break, 20min 6 15:40-16:20 Structural Methods for Equivalence Checking of Analog Circuits with Strong Nonlinearities L. Hedrich and S. Steinhorst (University of Frankfurt/Main, Germany) Invited talk 16:20-17:00 A Digital Verifier’s Peek into the Analog World Victor Konrad (Rambus Inc. USA) 

• Type: Journal
• Year: 2010
• Where: FMSD
• Authors: Kevin D. Jones, Victor Konrad, Dejan Nickovic
• Keywords: Analog Circuits, Cadence Research Labs, FMSD 2010, Statistical Model Checking