Architectural strategies for low-power VLSI turbo decoders

Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is required at very low signal-tonoise ratios (SNR). The problem of extracting the best coding gains from these kind of codes has been deeply investigated in the last years. Also the hardware implementation of turbo codes is a very challenging topic, mainly due to the iterative nature of the decoding process, which demands an operating frequency much higher than the data rate; in the case of wireless applications, the design constraints became even more strict due to the low-cost and low-power requirements. This paper first presents a new architecture for the decoder core with improved area and power dissipation properties; then partitioning techniques are proposed to reduce the power consumption of the decoder memories. It is proven that most of the power is dissipated by the large RAM units required by the decoder, ...

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Guido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni
• Keywords: Low Signal-tonoise Ratios, Power Dissipation Properties, Turbo Codes, TVLSI 2002