Architecture of Embedded Video Processing in a Multimedia Chip-Set

A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-window features with e.g. full-motion video, Internet and Teletext. To provide a large amount of computational power for such a full-featured application domain and to prevent the system from a communication bottleneck to the external memory, a heterogenous multi-processor architecture is implemented. The architecture offers a minimum of external communication overhead and enables programming on high functional level. The chip-set can simultaneously display e.g. two full-motion video windows, an Internet page and an additional mail indicator in front of a pixel-based wallpaper background. In addition, the video can be noise reduced and enhanced in sharpness together with a 50-100 Hz conversion to reduce field flicker.

• Type: Conference
• Year: 1999
• Where: ICIP
• Authors: Egbert G. T. Jaspers, Peter H. N. de With
• Keywords: Full-motion Video, Heterogenous Multi-processor Architecture, ICIP 1999, Image Processing, Video Display Processing