Architecture for a Non-deterministic Simulation Machine

Causality constraints of random discrete simulation make parallel and distributed processing difficult. Methods of applying reconfigurable logic to implement and accelerate simulation service event queues are presented which process simulation events at a rate of one event per 80 nanoseconds. The event generator presented in our previous work (Bumble and Coraor 1998) is also capable of sustaining the 80ns clock rate, providing overall speedup rates which depend on the software comparison scenario. The software comparison cited in this work provides a 2 order of magnitude speedup. The speedup factor varies with the size of the software event queue. Field Programmable Gate Arrays (FPGAs) are used to implement and test the service queue design.

• Type: Conference
• Year: 1998
• Where: WSC
• Authors: Marc Bumble, Lee D. Coraor
• Keywords: Event Queue, Modeling And Simulation, Simulation Service Event, Software Comparison, WSC 1998