Area estimation and optimisation of FPGA routing fabrics

This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for exploring design spaces suffer from expensive computation time, which is exacerbated by increased dimensionality due to the larger number of architectural parameters. In this paper we build on previously published work to describe a model of FPGA routing area. This model is used in conjunction with a form of optimisation known as geometric programming, in order to analytically derive optimised FPGA architectural parameters, demonstrating the power and accuracy of model-based approaches in configurable architecture design. We show that routing parameters such as connection and switch box flexibilities can be architected to save around 6% of area instead of using traditional “rules of thumb”.

• Type: Conference
• Year: 2009
• Where: FPL
• Authors: Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
• Keywords: Architectural Parameters, FPGA Routing Area, FPGA Routing Fabrics, FPL 2009, Hardware