Automated Extraction of Structural Information from SystemC-based IP for Validation

The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large percentage of the overall design time. The immediate solution is to automate certain procedures of generating testbenches from the design given certain information about the model. However, the volatile nature of models used for design exploration results in the designer having to alter the testbenches or the automation for the testbenches to reflect the design changes. In efforts to alleviate this problem of constantly changing designs and generating appropriate testbenches for the changed design, we propose a methodology of using structural reflection to extract structural information from design sources allowing the use of tools such as testbench generators and model viewers to seamlessly employ this extracted information. In this paper we present a methodology to automatically extract structural informa...

• Type: Conference
• Year: 2005
• Where: MTV
• Authors: David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla
• Keywords: Design, Hardware, Level Design Models, MTV 2005, Overall Design Time