Automatic generation of test sets for SBST of microprocessor IP cores

Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test solution since it guarantees high fault coverage figures, runs atspeed, and matches core test requirements while exploiting lowcost ATEs. However, automatically generating test programs is still an open problem. This paper presents a novel approach for test program generation, that couples evolutionary techniques with hardware acceleration. The methodology was evaluated targeting a 5-stage pipelined processor implementing a SPARCv8 microprocessor core. Categories and Subject Descriptors J.6 [COMPUTER-AIDED ENGINEERING]: Computer-aided design (CAD). General Terms Algorithms, Performance, Design, Experimentation, Verification. Keywords Automatic Test Generation, Test programs, Microprocessor Test, Pipelined Architectures, FPGA, Hardware Acce...

• Type: Conference
• Year: 2005
• Where: SBCCI
• Authors: Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
• Keywords: Attractive Test Solution, Microprocessor Core, SBCCI 2005, Test Programs