Automatic High Level Assertion Generation and Synthesis for Embedded System Design

SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge of designing and verifying present day complex systems. However, the gap between the definition of system specifications and design validation assertions that formally describe embedded system properties poses a challenge for HDL design engineers. We describe a prototype tool that utilizes UML as a system specification language and automatically generates SystemVerilog assertions for hardware design correctness validation with a corresponding Verilog module describing the hardware. An example is provided for a controller specified in UML with the resultant Verilog-RTL description and SystemVerilog assertion file produced automatically.

• Type: Conference
• Year: 2007
• Where: FDL
• Authors: Lun Li, Frank P. Coyle, Mitchell A. Thornton
• Keywords: Design Validation Assertions, FDL 2007, HDL Design Engineers, Systemverilog Assertion