Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs

—This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and tree-based lookahead architectures. Intrusion detection for network security is a compute-intensive application demanding high system performance. The tools implement and automate a customizable flow for the creation of efficient Field Programmable Gate Array (FPGA) architectures using system-level optimizations. Our methodology allows for customized performance through more efficient communication and extensive reuse of hardware components for dramatic increases in area-time performance.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Zachary K. Baker, Viktor K. Prasanna
• Keywords: Efficient Intrusion Detection, FPL 2004, Graph-based Partitioning Methodology, Intrusion Detection