Automatic Verification of External Interrupt Behaviors for Microprocessor Design

Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This paper proposes a CAD tool, called PEVT, to verify the external interrupt behaviors of microprocessors. An architecture description language extension, called EXPDL, is developed for the designer to capture the external interrupt behaviors for the microprocessor. PEVT is responsible to generate the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of ARM7 microprocessor core, which has had a SoC test chip and software porting including MP3 decoder and uC-OSII. PEVT successfully identified several sophisticated remaining bugs with only less than 88,000 cycles of RTL simulation with executi...

• Type: Conference
• Year: 2007
• Where: DAC
• Authors: Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang
• Keywords: DAC 2007, Design Automation, External Interrupt Behaviors, External Interrupt Verification, Verification Keywords Microprocessor