Balancing Bounded Treewidth Circuits

Algorithmic tools for graphs of small treewidth are used to address questions in complexity theory. For both arithmetic and Boolean circuits, it is shown that any circuit of size nO(1) and treewidth O(logi n) can be simulated by a circuit of width O(logi+1 n) and size nc , where c = O(1), if i = 0, and c = O(log log n) otherwise. For our main construction, we prove that multiplicatively disjoint arithmetic circuits of size nO(1) and treewidth k can be simulated by bounded fan-in arithmetic formulas of depth O(k2 log n). From this we derive the analogous statement for syntactically multilinear arithmetic circuits, which strengthens the central theorem of [MR08]. As another application, we derive that constant width arithmetic circuits of size nO(1) can be balanced to depth O(log n), provided certain restrictions are made on the use of iterated multiplication. Also from our main construction, we derive that Boolean bounded fan-in circuits of size nO(1) and treewidth k can be simulated b...

• Type: Conference
• Year: 2010
• Where: CSR
• Authors: Maurice Jansen, Jayalal M. N. Sarma
• Keywords: Arithmetic Circuits, CSR 2010, Disjoint Arithmetic Circuits, Log N, Theoretical Computer Science