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ICASSP
2010
IEEE

Bandwidth-intensive FPGA architecture for multi-dimensional DFT

13 years 10 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Although there are many efficient software solutions, they are not suitable for applications that require fast response time. In this paper we focus on FPGA-based implementation of MD DFT. The proposed architecture is based on a decomposition algorithm that takes into account FPGA resources and the characteristics of off-chip memory access, namely, the burst access pattern of the Synchronous Dynamic RAM (SDRAM). The architecture can support 2D, 3D, and even higher dimensional DFT with high performance. It has been implemented on a Xilinx Virtex-5 FPGA platform and its performance for 2D and 3D DFT measured and analyzed.
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija
Added 11 Feb 2011
Updated 11 Feb 2011
Type Journal
Year 2010
Where ICASSP
Authors Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vijaykrishnan Narayanan
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