BIST Based Interconnect Fault Location for FPGAs

This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduced. This procedure forms the first step of a new interconnect defect tolerant scheme that offers the possibility of using larger and more cost effective devices that contain interconnect defects without compromising on performance or configurability.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
• Keywords: FPL 2004, Interconnect Defect Tolerant, Interconnect Defects, Interconnect Fault