Block alignment in 3D floorplan using layered TCG

In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as technology advances into the deep submicron era. 3D chip is a feasible solution to these problems. It has been shown that interconnect lengths can be greatly reduced in 3D ICs. In this paper, a novel 3D floorplan representation namely Layered Transitive Closure Graph (LTCG) is proposed, which is based on the Transitive Closure Graph (TCG) representation for 2D non-slicing floorplans. In LTCG, we can impose topological relationships between both blocks of the same layer and blocks of different layers. Experimental results have shown that LTCG is very promising for multi-layer floorplanning and can handle the inter-layer alignment problem effectively. Categories and Subject Descriptors B.7.2 [Integrated Circuites]: Design aids—Placement and routing; J.6 [Computer Applications]: Computer-aided design—Comp...

• Type: Conference
• Year: 2006
• Where: GLVLSI
• Authors: Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching
• Keywords: GLVLSI 2006, Long On-chip Wires, Modern Ic Design, Transitive Closure Graph, VLSI