Branchless cycle prediction for embedded processors

Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branch instruction among those fetched. In this work we introduce Branchless Cycle Prediction (BLCP) to exploit this design inefficiency. BLCP uses a simple power efficient structure to predict cycles where there is no branch instruction among those fetched, at least one cycle in advance. We avoid accessing BTB during such cycles. We show that, by using BLCP, it is possible to reduce BTB power dissipation by 32% while paying a negligible performance cost (average: 0.2%). Categories and Subject Descriptors

• Type: Conference
• Year: 2006
• Where: SAC
• Authors: Kaveh Jokar Deris, Amirali Baniasadi
• Keywords: Applied Computing, Branch Instruction, Branch Target, Branch Target Buffer, SAC 2006