Bridging the computation gap between programmable processors and hardwired accelerators

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper, we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is the...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke
• Keywords: Better Power Efficiency, Computer Architecture, HPCA 2009, Loop Accelerator Architecture, Semi-programmable Loop Accelerator