Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+

Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such systems have demonstrated superior performance and reduced energy consumption versus their traditional counterparts based on microprocessors. However, most of such work has been limited to small system sizes. Unlike traditional HPC systems, lack of integrated, system-wide, parallel-programming models and languages presents a significant design challenge for creating applications targeting scalable, reconfigurable HPC systems. In this paper, we introduce and investigate a novel programming model based on Partitioned Global Address Space (PGAS), which simplifies development of parallel applications for such systems. The new multilevel PGAS programming model captures the unique characteristics of these systems, such as the existence of multiple levels of memory hierarchy and heterogeneous computation resources. To ev...

• Type: Conference
• Year: 2009
• Where: SC
• Authors: Vikas Aggarwal, Alan D. George, K. Yalamanchili, C. Yoon, Herman Lam, Greg Stitt
• Keywords: Applied Computing, Hpc System, Reconfigurable Hpc Systems, SC 2009, Traditional Hpc Systems