Buffer management for multi-application image processing on multi-core platforms: Analysis and case study

Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient management of buffer memory is critical to multi-core image processing. To address this problem, this paper develops new modeling and analysis techniques based on dataflow representations, and demonstrates these techniques on a multi-core implementation case study involving multiple, concurrently-executing image processing applications. Our techniques are based on careful representation and exploitation of frame- or block-based operations, which involve repeated invocations of the same computations across regularly-arranged subsets of data. Using these new approaches to manage block-based image data, this paper demonstrates methods to analyze synchronization overhead and FIFO buffer sizes when mapping image processing applications onto heterogeneous, multi core architectures.

• Type: Conference
• Year: 2010
• Where: ICASSP
• Authors: Dong-Ik Ko, Nara Won, Shuvra S. Bhattacharyya
• Keywords: Block-based Image Data, ICASSP 2010, Image, Multi-core Implementation Case, Signal Processing