A C compiler for a processor with a reconfigurable functional unit

This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that can extract computations from applications to put into the RFU. The results show that large instruction sequences can be created and extracted by these techniques. An average speedup of 2.6 is achieved over a set of benchmarks.

• Type: Conference
• Year: 2000
• Where: FPGA
• Authors: Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee
• Keywords: FPGA, FPGA 2000, Large Instruction Sequences, Mixed Processor/fpga Architecture, Reconfigurable Functional Unit