Carbon: architectural support for fine-grained parallelism on chip multiprocessors

Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CMP, applications must expose their thread-level parallelism to the hardware. One common approach to doing this is to decompose a program into parallel “tasks” and allow an underlying software layer to schedule these tasks to different threads. Software task scheduling can provide good parallel performance as long as tasks are large compared to the software overheads. We examine a set of applications from an important emerging domain: Recognition, Mining, and Synthesis (RMS). Many RMS applications are compute-intensive and have abundant thread-level parallelism, and are therefore good targets for running on a CMP. However, a significant number have small tasks for which software task schedulers achieve only limited parallel speedups. We propose Carbon, a hardware technique to accelerate dynamic task schedu...

• Type: Conference
• Year: 2007
• Where: ISCA
• Authors: Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen
• Keywords: Hardware, ISCA 2007, Software Task, Software Task Schedulers, Task Scheduling