Carbon nanotube transistor circuits: models and tools for design and performance optimization

In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier is presented. The model enables device design and performance optimization.

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan
• Keywords: Carbon Nanotube Transistor, Hardware, ICCAD 2006, Mode Nanotube Transistor, Nanotube Transistor Circuits