On the Characterization of Multi-Point Nets in Electronic Designs

Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those properties is essential for improving placement and routing techniques for digital circuits. Previous work on estimating design properties failed to take multi-point nets into account. All nets were assumed to be 2-point nets (especially for estimating the number of nets). In this paper, we aim at characterizing multi-point nets in electronic designs. We will develop a model for the behaviour of multi-point nets during the partitioning process. The resulting distribution of nets over their net degree will be validated through comparison with benchmark data.

• Type: Conference
• Year: 1998
• Where: GLVLSI
• Authors: Dirk Stroobandt, Fadi J. Kurdahi
• Keywords: 2-point Nets, Electronic Designs, GLVLSI 1998, Multi-point Nets, VLSI