On-chip inductance cons and pros

Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slower CAD tools as compared to RC-based tools. Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty. The viability of design methodologies considering on-chip inductance is briefly discussed. I. HISTORICAL PERSPECTIVE HISTORICALLY, the gate parasitic impedances have been much larger than the interconnect parasitic impedances since the gate geometries (the width and length) were quite large (about 5 m was a typical minimum feature size in 1980). Thus, interconnect parasitic impedances have historically been negle...

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: Yehea I. Ismail
• Keywords: Interconnect, On-chip Inductance, Parasitic Impedances, TVLSI 2002