CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells

We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width Wcell. Then, another model generates a 2-D layout that has width Wcell and requires a minimum number of routing tracks. Run times are in seconds for circuits with up to 16 transistors. For larger circuits, we extend CLIP to a hierarchical method HCLIP that places series-connected transistors contiguously. This reduces run times by up to three orders of magnitude, and still yields optimal results in over 80% of cases.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Avaneendra Gupta, John P. Hayes
• Keywords: 2-D Layout, Computer Architecture, DAC 1997, Minimum Width Wcell, Width Wcell