A code motion technique for accelerating general-purpose computation on the GPU

Recently, graphics processing units (GPUs) are providing increasingly higher performance with programmable internal processors, namely vertex processors (VPs) and fragment processors (FPs). Such newly added capabilities motivate us to perform general-purpose computation on GPUs (GPGPU) beyond graphics applications. Although VPs and FPs are connected in a pipeline, many GPGPU implementations utilize only FPs as a computational engine in the GPU. Therefore, such implementations may result in lower performance due to highly loaded FPs (as compared to VPs) being a performance bottleneck in the pipeline execution. The objective of our work is to improve the performance of GPGPU programs by eliminating this bottleneck. To achieve this, we present a code motion technique that is capable of reducing the FP workload by moving assembly instructions appropriately from the FP program to the VP program. We also present the definition of such movable instructions that do not change the I/O speci�...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: T. Ikeda, Fumihiko Ino, Kenichi Hagihara
• Keywords: Distributed And Parallel Computing, FP Workload, IPPS 2006, Performance, Programmable Internal Processors