Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers

: A brief review of mapping generalized template matching operations onto reconfigurable computers is given. A combinatorial optimization process, where the objective is to minimize the FPGA computation time and the constraint is the FPGA board resources, is a key step of the whole mapping process. This paper presents algorithms for solving the optimization problem and experimental results.

• Type: Conference
• Year: 2006
• Where: ERSA
• Authors: Xuejun Liang, Qutaibah M. Malluhi
• Keywords: Combinatorial Optimization Process, ERSA 2006, ERSA 2007, FPGA Computation Time, Template Matching Operations