Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits

Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling allows us to model the communication patterns among the components, analyze the impact of interconnect latency on the overall data processing throughput, and manage computation/communication tradeoffs to optimize the performance of the system. In this paper, we present recycling as a circuit-level design technique for optimizing the performance of sequential circuits beyond what can be achieved by retiming. We also provide a theoretical framework to guide the simultaneous application of the two techniques. Our model identifies the conditions under which an optimally-retimed synchronous circuit can be further sped-up and determines the amount of the resulting performance gain.

• Type: Conference
• Year: 2003
• Where: SBCCI
• Authors: Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
• Keywords: Design Technique, Recycling, SBCCI 2003, System-level Design Technique