Communication speed selection for embedded systems with networked voltage-scalable processors

High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power efficiency. Many such interfaces also support multiple data rates, and this ability is opening a new dimension in the power/performance trade-offs between communication and computation on voltage scalable embedded processors. To minimize energy consumption in these networked architectures, designers must not only perform functional partitioning but also carefully balance the speeds between communication and computation, which compete for time and energy. Minimizing communication power without considering computation may actually lead to higher energy consumption at the system level due to elongated on-time as well as lost opportunities for dynamic voltage scaling on the processors. We propose a speed selection methodology for globally optimizing the energy consumption in embedded networked architectures. We fo...

• Type: Conference
• Year: 2002
• Where: CODES
• Authors: Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
• Keywords: CODES 2002, Energy Consumption, Hardware, Networked Architectures, Speed Selection