Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines

This paper presents new achievements on the automatic mapping of algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation- and functional-level parallelism, and speculative execution. Such expositions are efficiently represented by an hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied.

• Type: Conference
• Year: 2001
• Where: FPL
• Authors: João M. P. Cardoso, Horácio C. Neto
• Keywords: Field-programmable Gate Array, Flow Exposes Operation, FPL 2001, Hardware, Reconfigurable Hardware Element