Compiled-code-based simulation with timing verification

Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven strategy is the best approach for high-performance simulation engines. However, proponents of the table-driven strategy for simulation engines claim that concerning timing simulation the advantage of the compiler-driven strategy only exists for zero-delay and unitdelay simulation but there would be no competition concerning nominal-, fixed-, and precise-delay simulation. It is the intention of this paper to contradict this claim by proving that all types of timing models can be defined in an algebraic way and compiled into code for the Munich Simulation Computer, an event-flow computer for highperformance compiler-driven logic simulation. Experimental results are presented and discussed concerning code size as well as code execution overhead. Keywords Timing Verification, Compiler-Driven Logic Simulation, Upd...

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: Winfried Hahn, Andreas Hagerer, C. Herrmann
• Keywords: Compiler-driven Logic Simulation, EURODAC 1994, Simulation, Simulation Engines, VHDL