Compiler-Assisted Memory Encryption for Embedded Processors

A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of the decryption operation that must precede a load requiring an off-chip memory access, decryption being on the critical path, can significantly degrade performance. Recently hardware counter-based one-time pad encryption techniques [11, 13, 9] have been proposed to reduce this overhead. For highend processors the performance impact of decryption has been successfully limited due to: presence of fairly large on-chip L1 and L2 caches that reduce off-chip accesses; and additional hardware support proposed in [13, 9] to reduce decryption latency. However, for low- to medium-end embedded processors the performance degradation is high because first they only support small (if any) on-chip L1 caches thus leading to significant off-chip accesses and second the hardware cost of decryption latency reduction solut...

• Type: Conference
• Year: 2007
• Where: HIPEAC
• Authors: Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
• Keywords: Decryption, Embedded Processor, HIPEAC 2007, Memory Encryption, System Software