Compiler-Directed Dynamic Frequency and Voltage Scheduling

Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies opportunities for dynamic voltage and frequency scaling of the CPU without significant increase in overall program execution time. The paper introduces a simple, yet effective performance model to determine an efficient CPU slow-down factor for memory bound loop computations. Simulation results of a superscalar target architecture and a program kernel compiled at different optimizations levels show the potential benefit of the proposed compiler optimization. The energy savings are reported for a hypothetical target machine with power dissipation characteristics similar to Transmeta's Crusoe TM5400 processor.

• Type: Conference
• Year: 2000
• Where: PACS
• Authors: Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
• Keywords: Dynamic Voltage, Frequency Scaling, Hardware, PACS 2000, Power Dissipation