Compiler-optimized usage of partitioned memories

In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use of caches in the memory hierarchy, processor cores today also include small onchip memories called scratchpad memories whose usage is not controlled by hardware, but rather by the programmer or the compiler. Techniques for utilization of these scratchpads have been known for some time. Some new processors provide more than one scratchpad, making it necessary to enhance the workflow such that this complex memory architecture can be efficiently utilized. In this work, we present an energy model and an ILP formulation to optimally assign memory objects to different partitions of scratchpad memories at compile time, achieving energy savings of up to 22% compared to previous approaches.

• Type: Conference
• Year: 2004
• Where: WMPI
• Authors: Lars Wehmeyer, Urs Helmig, Peter Marwedel
• Keywords: Hardware, Memories Called Scratchpad, Memory Architecture, Scratchpad Memories, WMPI 2004