This paper presents an overview of a prototype hardware compiler which compiles a design expressed in the Ruby language into FPGAs. The features of two important modules, the re nement module and the oorplanning module, are discussed and illustrated. Target code can be produced in various formats, including device-speci c formats such as XNF or CFG, and device-independent formats such as VHDL. The viability of our oorplanning scheme is demonstrated by a compiler backend for Algotronix's CAL1024 FPGAs. The implementation of a priority queue is used to illustrate our approach.