Completeness and Nondeterminism in Model Checking Transactional Memories

Software transactional memory (STM) offers a disciplined concurrent programming model for exploiting the parallelism of modern processor architectures. This paper presents the first deterministic specification automata for strict serializability and opacity in STMs. Using an antichain-based tool, we show our deterministic specifications to be equivalent to more intuitive, nondeterministic specification automata (which are too large to be determinized automatically). Using deterministic specification automata, we obtain a complete verification tool for STMs. We also show how to model and verify contention management within STMs. We automatically check the opacity of popular STM algorithms, such as TL2 and DSTM, with a universal contention manager. The universal contention manager is nondeterministic and establishes correctness for all possible contention management schemes.

• Type: Conference
• Year: 2008
• Where: CONCUR
• Authors: Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
• Keywords: CONCUR 2008, Deterministic Specification, Deterministic Specification Automata, Distributed And Parallel Computing, Universal Contention Manager