Complexity Analysis and Performance Evaluation of Matrix Product on Multicore Architectures

The multicore revolution is underway, bringing new chips introducing more complex memory architectures. Classical algorithms must be revisited in order to take the hierarchical memory layout into account. In this paper, we aim at minimizing the number of cache misses paid during the execution of the matrix product kernel on a multicore processor, and we show how to achieve the best possible tradeoff between shared and distributed caches. Comprehensive simulation results confirm the analytical performance predictions and fully establish the practical significance of our new algorithms.

• Type: Conference
• Year: 2009
• Where: ICPP
• Authors: Mathias Jacquelin, Loris Marchal, Yves Robert
• Keywords: Complex Memory Architectures, Distributed And Parallel Computing, Hierarchical Memory Layout, ICPP 2009, Multicore Revolution