Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping

We consider technology mapping from factored form binary leaf-DAG to lookup tables LUTs, such as those found in eld programmable gate arrays. Polynomial time algorithms exist for in the worst case optimal mapping of a single-output function. The worst case occurs when the leaf-DAG is a tree. Previous results gave a tight upper bound on the number of LUTs required for LUTs with up to 5 inputs and a bound with 6 inputs. The bounds are a function of the number of literals and the LUT size. We extend these results to tight bounds for LUTs with an arbitrary number of inputs.

• Type: Conference
• Year: 2000
• Where: IPPS
• Authors: Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi
• Keywords: Case Optimal Mapping, Distributed And Parallel Computing, Eld Programmable Gate, IPPS 2000, Tight Upper Bound