Configuration Compression for the Xilinx XC6200 FPGA

One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration. Configuration Compression When FPGAs were first introduced in the mid 1980s they were viewed as a technology for replacing standard gate arrays for some applications. In these first generation systems, a single configuration is created for the FPGA, and this configuration is the only one loaded into the FPGA. A second generation soon followed, with FPGAs that could use multiple configu...

• Type: Conference
• Year: 1998
• Where: FCCM
• Authors: Scott Hauck, Zhiyuan Li, Eric J. Schwabe
• Keywords: FCCM 1998, FPGA, Run-time Reconfiguration, Series Fpga Architecture, VLSI