Considering process variations during system-level power analysis

Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic levels. However, as the magnitude of process variations increases, their effects will need to be addressed earlier in the design cycle. In this paper, we propose techniques for accurately and efficiently incorporating the effects of process variations into systemlevel power estimation tools. To motivate our work, we first study the impact of process variations on the power consumption of an example System-on-Chip (SoC). We consider simple extensions of current approaches to system-level power estimation (spreadsheetbased and simulation-based power estimation), and demonstrate their limitations in performing variation-aware power estimation. We propose a system-level power estimation methodology that can accurately and efficiently an...

• Type: Conference
• Year: 2006
• Where: ISLPED
• Authors: Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
• Keywords: ISLPED 2006, Power Estimation, Process Variations, System-level Power Estimation