Contention-Conscious Transaction Ordering in Embedded Multiprocessors

This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are non-negligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and non-iterative execution. We develop new heuristics for finding efficient transaction orders, and perform an experimental comparison to gauge the performance of these heuristics.

• Type: Conference
• Year: 2000
• Where: ASAP
• Authors: Mukul Khandelia, Shuvra S. Bhattacharyya
• Keywords: ASAP 2000, Hardware, Interprocessor Communication Operations, Iterative Dataflow Graphs, Transaction Orders